Field of the Invention
The present invention relates to electronics and, more specifically but not exclusively, to integrated circuits having defects in their scan-test circuitry, including, but not limited to, scan-chain defects.
Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
It is well known to design an integrated circuit (IC), such as (without limitation) a field-programmable gate array (FPGA), with scan-test circuitry that supports scan testing of the integrated circuitry to detect defects in the functionality of that integrated circuitry. Scan testing typically involves synthesizing scan chains in hard logic blocks embedded in the integrated circuit by replacing regular flip-flop cells with scan flip-flops and then stitching them together into one or more scan chains. A scan chain is a sequence of interconnected scan flip-flops that enables an input data pattern to be shifted into and applied to integrated circuitry under scan testing (also known as CUST) consisting of combinational and sequential logic, where the resulting data generated by the CUST is shifted out by the scan chain to determine whether the CUST is functioning properly, e.g., by comparing the resulting data to an expected set of data. Note that, since the scan flip-flops of a scan chain typically support both scan-test functionality as well as normal data-processing functionality of the integrated circuit, scan chains are typically considered to be part of the CUST.
FIG. 1 is a simplified block diagram of a portion of an exemplary scan chain used to support scan testing of a block of combinational logic. In particular, FIG. 1 shows three scan flip-flops 110 variously connected to five interconnected logic gates 120. A typical scan chain will have many more analogously connected scan flip-flops. Each intermediate scan flip-flop 110 along the scan chain has a (2×1) multiplexer (mux) 112 and a flip-flop (FF) cell 114, where one mux input is connected to receive the output of one of the CUST logic gates 120 at the Q input node of the scan flip-flop 110, the other mux input is connected to receive the data output Q of the previous scan flip-flop 110 at the SI input node of the present scan flip-flop 110, and the multiplexer output is connected to the data input port D of the FF cell 114 of the present scan flip-flop 110. Each scan flip-flop 110 also receives a scan-enable control signal SE that controls the selection made by the mux 112 and a clock signal CLK that controls the operation of the FF cell 114, e.g., shifting data applied at the cell's data input port D to the cell's data output port Q at every rising and/or falling edge of the clock signal CLK. In addition to being connected to the SI input node of the next scan flip-flop 110, the data output port Q of the FF cell 114, which is also the data output node Q of the present scan flip-flop 110, is also connected to an input of the one of the CUST logic gates 120.
Scan testing of the CUST may be performed as follows. When the scan enable signal SE is set to select data appearing at the SI input ports of the scan flip-flops 110, a scan-test pattern can be sequentially clocked into the scan chain. After the scan-test pattern has been completely clocked into the scan chain, such that each scan flip-flop 110 stores a different bit of the scan-test pattern, the scan enable signal SE can be reset to select the resulting CUST data appearing at the D input ports of the scan flip-flops. At this point, each scan flip-flop 110 stores a different bit of the resulting CUST data pattern. The scan enable signal SE can again be set to select the data appearing at the SI input ports to sequentially read the resulting CUST data pattern out from the scan chain for comparison with the expected CUST data pattern to identify potential CUST defects, and to simultaneously shift in the next scan test pattern (if any) bit-by-bit into the scan chain.
After the scan chains are synthesized, an automatic test pattern generator (ATPG) tool is employed to analyze the circuit and compute the test vectors needed to achieve high coverage. Shift patterns containing these test vectors are serially shifted through the scan chains into the CUST, and the CUST responses to these patterns are captured and shifted out through the scan chains and analyzed by the ATPG tool. Sometimes, the coverage achieved with this targeted structural test approach is close to 100% if the RTL (register-transfer level) for the CUST has been well designed, passes all scan design rules, and achieves functional and scan-mode timing closure verified via static timing analysis after the backend design (consisting of logic synthesis, place-and-route).
Therefore, even after all scan design rules for assuring high coverage are obeyed during front-end logic design, scan chains can be successful at achieving high coverage only if (a) the scan chains do not have timing problems after backend design (such as hold-time problems during shift due to not achieving timing closure in scan-test mode, or hold-time problems due to lockup latches with the wrong polarity) and (b) all auxiliary, constrained signals needed for scan testing of a logic block and generated by other logic blocks or from top-level signal hookups after chip integration are in their expected states. Sometimes, it is highly challenging to meet these requirements (particularly on designs with multiple functional clock domains) due to the design complexity, design revisions late in the design cycle, and the time-to-market pressure.
Although a scan chain is designed to support scan testing to determine whether there are any defects in the CUST, the fact is that there may be defects in the scan chain itself. There are a number of different types of scan-chain defects that can occur along a scan chain.
FIG. 2 is a simplified block diagram of a portion of a scan chain that is susceptible to a particular type of scan-chain defect known as a hold-time violation. FIG. 2 shows two sequential scan flip-flops 210(1) and 210(2) that are analogous to the scan flip-flops 110 of FIG. 1, where the D input node of each scan flip-flop 210 is connected to the output of a different set of functional logic 220 and the Q output node of the first (aka launch) scan flip-flop 210(1) is connected to the SI input node of the second (aka capture) scan flip-flop 210(2).
As shown in FIG. 2, the clock signal applied to the CLK input node of the first scan flip-flop 210(1) is routed via a first clock-distribution network 230(1), while the clock signal applied to the CLK input node of the second scan flip-flop 210(2) is routed via a second clock-distribution network 230(2). Although, during scan testing, the same scan-test clock is selected for both scan flip-flops 210, because that scan-test clock is routed via two different clock-distribution networks 230(1) and 230(2), there may be timing skew between the two versions of that scan-test clock applied to the two scan flip-flops 210. Such timing skew may result due to incorrect timing constraints used during static timing analysis or by the failure of the place-and-route tool to close timing with the correct timing constraints. If the clock signal applied to the first scan flip-flop 210(1) arrives too early, e.g., before the clock signal is applied to the second scan flip-flop 210(2), then the new Q data output signal from the first scan flip-flop 210(1) may appear at the SI data input node of the second scan flip-flop 210(2) before the existing Q data from the first scan flip-flop 210(1) received at the SI data input node of the second scan flip-flop 210(2) has been correctly processed by second scan flip-flop 210(2) and shifted to its output. In other words, the data output from the first scan flip-flop 210(1) is appearing too soon at the SI data input of the second scan flip-flop 210(2) and erasing the data that should have been processed by the second scan flip-flop 210(2). In that case, a hold-time violation will occur which may result in a loss of data.
When such a hold-time violation is detected during the design of an integrated circuit, the design of the integrated circuit is modified to ensure that the hold-time violation does not occur. This design modification may involve making mask revisions, which typically requires a backend design engineer to successfully close timing in scan-test mode and correct all the other design problems that cause scan-test problems, and is therefore very time consuming and costly in terms of non-recurring engineering (NRE) resources and mask costs. Even if this problem is detected before chip manufacture (thereby avoiding costly mask revisions), the time-to-market pressure makes it highly challenging and expensive to correct timing and logical problems that occur in scan-test mode due to late design revisions.
FIG. 3 is a simplified block diagram of a portion of a scan chain that is susceptible to a second type of scan-chain defect known as polarity reversal, in which a signal of the wrong polarity is applied within a scan chain. The particular situation represented in FIG. 3 is of a scan chain that crosses from one clock domain (Clock1) having a first clock-distribution network 330(1) to a different clock domain (Clock2) having a second clock-distribution network 330(2). In FIG. 3, scan flip-flops 310(1) and 310(2) are in the domain of Clock1, while scan flip-flop 310(3) is in the domain of Clock2.
In order to ensure that the transition from the Clock1 domain to the Clock2 domain functions properly, the scan chain should satisfy the well-known NICE (next instance clocked concurrently or earlier) principle. It is known to configure a lockup latch 340 between the last scan flip-flop 310(2) in the Clock1 domain and the first scan flip-flop 310(3) in the Clock2 domain in order to add a one-half clock cycle delay and satisfy the NICE principle. In the particular implementation of FIG. 3, the lockup latch 340 is a positive-level latch, and the scan chain includes an inverter 350 that ensures that the lockup latch 340 is properly controlled by the level of an inverted version of Clock1. Note that, if lockup latch 340 is a negative-level latch, then inverter 350 is omitted, and the lockup latch 340 is properly controlled by the level of Clock1 itself.
Assume that the scan chain of FIG. 3 is originally designed such that (i) the lockup latch 340 is a positive-level latch and (ii) the scan chain has the inverter 350. If, for some reason, the design is subsequently changed, e.g., during scan synthesis, to use a negative-level latch instead of a positive-level latch for lockup latch 340, then the inverter 350 will need to be removed from the design. Similarly, if the scan chain of FIG. 3 were originally designed such that (i) the lockup latch 340 is a negative-level latch and (ii) the scan chain has no inverter like inverter 350, and then, for some reason, the design is subsequently changed to use a positive-level latch instead of a negative-level latch for lockup latch 340, an inverter like inverter 350 will need to be added to the design. If the particular polarity of the lockup latch 340 does not match the presence/absence of the inverter 350, then a polarity-reversal scan-chain defect will exist, and the scan chain might not operate properly. As such, when the polarity of the lockup latch 340 is changed, the design of the integrated circuit is further modified to accommodate that change, e.g., by removing or adding an inverter. Here, too, such modification may involve making costly and time-consuming mask revisions.
Another situation where a polarity-reversal defect can occur in scan-test circuitry is when a scan-test control signal or other constrained scan-test input signal of the wrong polarity is applied to scan-test control circuitry that controls the scan testing within an integrated circuit.
FIG. 4 is a simplified block diagram showing a constrained signal 405 being applied to a block of scan-test control circuitry 410. As used herein, the term “scan-test control circuitry” includes any circuitry that contributes to the control of scan testing. The circuitry that generates the constrained signal 405 is external to the CUST and may be either internal to or external to the integrated circuit that contains the CUST. If, for some reason, the constrained signal 405 has the wrong polarity, then the scan testing of the CUST implemented by the scan-test control circuitry 410 may be improper.
When scan-test defects like the ones described above in the context of FIGS. 2-4 are detected after the integrated circuit mask set has been generated, then the IC mask set is revised in order to correct and/or avoid the scan-test defects. This can significantly increase both the time and cost of designing integrated circuits.